The present invention relates to a method for manufacturing a phase change memory device, and more particularly, to a method for manufacturing a phase change memory device which can stably form an interface between a lower electrode contact and a phase change layer.
In general, memory devices are largely divided into a volatile RAM (random access memory), which loses inputted information when power is interrupted and a non-volatile ROM (read-only memory), which can continuously maintain the stored state of inputted information even when power is interrupted. When considering the volatile RAM, a DRAM (dynamic RAM) and when considering SRAM (static RAM) can be mentioned, and as the non-volatile ROM, a flash memory device such as an EEPROM (electrically erasable and programmable ROM) can be mentioned.
As is well known in the art, while the DRAM is an excellent memory device, the DRAM must have high charge storing capacity, and to this end, since the surface area of an electrode must be increased, it is difficult to accomplish a high level of integration. Further, in the flash memory device, due to the fact that two gates are stacked on each other, a high operation voltage is required when compared to a source voltage. As a result a separate booster circuit is needed to form the voltage necessary for write and delete operations, making it difficult to accomplish a high level of integration.
To improve upon the current memory devices, researches have been making an effort to develop a novel memory device having a simple configuration and capable of accomplishing a high level of integration while retaining the characteristics of the non-volatile memory device. A phase change memory device recently disclosed in the art is a product of this effort.
In the phase change memory device, a phase change, which occurs in a phase change layer interposed between a lower electrode and an upper electrode from a crystalline state to an amorphous state is due to current flow between the lower electrode and the upper electrode. The information stored in a cell is recognized by the medium of a difference in resistance between the crystalline state and the amorphous state.
In detail, in the phase change memory device, a chalcogenide layer being a compound layer made of germanium (Ge), stibium (Sb) and tellurium (Te) is employed as a phase change layer. As a current is applied, the phase change layer undergoes a phase change by heat, that is, Joule heat, between the amorphous state and the crystalline state. Accordingly, in the phase change memory device, when considering the fact that the specific resistance of the phase change layer in the amorphous state is higher than the specific resistance of the phase change layer in the crystalline state, in a read mode, whether the information stored in a phase change cell has a logic value of ‘1’ or ‘0’ is determined by sensing the current flowing through the phase change layer.
In a conventional phase change memory device, an oxide layer is formed to delimit a contact hole forming region for a lower electrode contact. However, in general, the oxide layer is not uniformly deposited over the entire substrate inducing a step. When etching the oxide layer to define a contact hole, the step on the oxide layer causes the contact hole to be non-uniformly defined, and therefore a lower electrode contact cannot be stably formed in the contact hole. As a result, in the conventional phase change memory device, due to the unstable state of the lower electrode contact, an interface between the lower electrode contact and the phase change layer becomes unstable as well, leading to non-uniformity of a programming current.
Further, in the conventional phase change memory device, due to limitations in the exposure process, it is difficult to form a lower electrode contact having a diameter less than a predetermined diameter. This leads to limitations in reducing the contact area between the lower electrode contact and the phase change layer. If due to the limitation in the exposure process, the diameter of a target lower electrode contact is less than the predetermined diameter, not only it is difficult to properly conduct a process for defining the contact hole for a lower electrode contact, but also the variation of the diameter of the contact hole increases making it difficult to manufacture a phase change memory device having uniform characteristics.